A. Field of the Invention
This invention relates generally to switching circuits and more particularly to an improved field effect transistor sample and hold switching circuit.
B. Description of the Prior Art
In general, field effect transistors are well suited for use in gate and switching circuits. A common approach utilizes as a switch a junction field effect transistor (JFET) designed to have a low ON resistance. The JFET gate must track the analog signal in the ON state to make sure that the switch stays on. This places severe demands on the gate switching circuits.
A major disadvantage of this use of JFETs in switching circuits has been the incidence of spurious transient responses in the source and drain circuit due to the control or gate signal. These spurious responses, in a form of transients are the result of charging and discharging of interelectrode capacitances between the gate and drain terminals and the gate and source terminals. For example, to switch the FET OFF, substantially the full supply voltage is used, which results in a large amount of interelectrode charge that must be switched to switch the state of the FET.
In the prior art a number of approaches have been utilized to reduce these transients. One method entails the use of complimentary FET devices. The major drawback inherent in this practice resides in the fact that it is prohibitively expensive to manufacture complimentary FETs having identical characteristics. Another prior art method prescribes that the FET be made to have interelectrode capacitances as small as possible. Reducing the physical size of the FET reduces the undesirable parasitic capacitances, but increases the resistance of the device when it is ON, a very undersirable effect in most applications.